The present disclosure relates generally to the manufacture of integrated circuit devices and, more particularly, to a method and structure for ultra-thin silicon-on-insulator isolation.
As the current integrated circuit (IC) technology moves to smaller feature sizes and the density of IC features in an IC substrate surface increases, shallow trench isolation (STI) processes are replacing local oxidation of silicon (LOCOS) isolation methods as the processes of choice for isolating active areas in semiconductor circuits. LOCOS methods are generally undesirable at sub-0.5 micron design rules because they typically introduce non-planarity and a so-called bird""s beak at the edge of an active area, which reduces the packing density of the circuitry. In contrast, STI process provide isolation schemes that produce a relatively high degree of planarity and eliminate the bird""s beak problems.
As shown in FIGS. 1-3, a conventional STI process generally includes a native oxide layer 12, e.g., silicon dioxide, that is blanket deposited onto a surface of an IC substrate. A polishing stop layer 14, e.g., silicon nitride (Si3N4) is then blanket deposited onto the native oxide layer 12. The polishing stop layer 14 and the native oxide layer 12 are etched through using conventional lithography well known to those skilled in the art to form trenches 16, 18, and 20 in the IC substrate. Trench 16 is formed in a wide open area and trenches 18, 20 are formed in a dense area of IC substrate 10. As shown, the dense area has a greater number of trenches per unit area of the IC substrate than the wide open area. Those skilled in the art will also recognize that the trenches 16 in the wide open area are also wider than the trenches 18, 20 in the dense area.
An insulating layer 22, e.g., an oxide, is then deposited onto the IC substrate 10 and fills the trenches 16, 18, and 20. As such, subsequently formed active areas are electrically isolated from one another. Deposition is typically effected by chemical vapor deposition or through the use of spin-on glasses. IC substrate 10 is then subjected to a chemical mechanical polishing process (CMP) to remove the insulating layer 22 and polish stop layer 14. CMP typically includes mounting an IC substrate face down on a holder and rotating the IC substrate face against a polishing pad mounted on a platen, which also rotates. During oxide CMP, a slurry composition, e.g., hydrogen peroxide, is introduced between the polishing pad and the IC substrate surface or on the polishing pad near the IC substrate surface to remove insulating layer 22. The presence of the polishing stop layer insures that after CMP oxide has concluded, an appropriate thickness of native oxide layer 14 is maintained above the substrate, which has a significant impact on performance characteristics of an IC As shown in FIG. 3, after oxide CMP is finished and the polishing stop layer 14 is removed, isolation structures (i.e., trenches 16, 18, and 20 filled with insulating material 22) are formed in the IC substrate, the native oxide layer 12 with the appropriate thickness is maintained above the IC substrate, and the substantially planar surface of insulating layer 22 above trenches 16, 18, and 20 is preserved.
Thus, in conventional STI processing, the isolation is performed prior to the gate process. Moreover, a degree of dishing may occur in trench 16 resulting in a concave section, which may provide an electrically conductive pathway leading to undesirable electrical leakage. In addition, a preclean step that is typically employed prior to epi growth can overreach then shallow trench isolation fill and expose silicon during the subsequent epi growth step. With this unwanted epi growth at or near the isolation, there is a potential for shorting across the isolation.
In addition to the use of STI isolation processes, current IC technology is gravitating to the use of a silicon-on-insulator (SOI) substrate. The main advantages of using an SOI substrate include, among others, a marked reduction in the parasitic capacitance, an increase in the switching speed, a greater immunity to noise, less leakage currents, no latch-up of parasitic components, greater resistance to radiation effects, and an increase on the component packaging density. As such, SOI substrates are applicable to fabrication of metal oxide semiconductor field effect transistors (MOSFETs) under the size of 0.1 micron due to its improvement on short channel effects, its intensive tolerance to radiation, associated simple fabrication process, and excellent device isolation properties.
However, as SOI film thickness scales to less than about 20 nanometers, the above noted conventional STI process present problems. For example, the oxide fill between active areas can be deleteriously etched by a subsequent suicide and/or raised source/drain wet cleaning processes. Moreover, poly strapping can occur at the SOI edge, which can cause threshold voltage (Vt) lowering in narrow width devices.
Disclosed herein is a method and structure for fabricating isolation regions on a SOI substrate. The method includes depositing a first oxide layer onto a SOI substrate, wherein the SOI substrate includes a buried oxide layer and a silicon layer disposed on the buried oxide layer, and wherein the silicon layer has a thickness of less than about 20 nanometers; depositing a first polysilicon layer onto the first oxide layer; etching selected portions of the first polysilicon layer, the first oxide layer, and the silicon layer to form isolation regions; depositing a conformal nitride layer onto the substrate; depositing a second oxide layer onto the nitride layer; polishing the substrate to the nitride layer, selectively etching the nitride layer to expose a surface of the polysilicon layer, wherein the isolation regions comprise the nitride layer and the oxide layer; cleaning the exposed surfaces of the polysilicon layer, depositing a second polysilicon layer in contact with the exposed surfaces of the first polysilicon layer.
A semiconductor device structure includes a SOI substrate comprising a buried oxide layer and a silicon layer disposed on the buried oxide layer, wherein the silicon layer has a thickness of less than about 20 nanometers; and an isolation region formed in the silicon layer providing electrical isolation between adjacent active devices formed on the SOI substrate, the isolation region comprising a nitride liner layer in contact with the buried oxide layer and a sidewall defining the active area, wherein the nitride liner layer is at a thickness less than about 50 nanometers.
The above described and other features are exemplified by the following figures and detailed description.